1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly to testing such devices.
2. Description of the Related Art
Advances in integrated circuit (IC) technology have given rise to IC devices with complex circuitry with hundreds of thousands of logic gates and operating frequencies in excess of 1 GHz. As the circuit complexity of a device increases, so does the need to thoroughly test the circuits. A general solution to the problem of testing integrated circuits is to embed test circuitry, commonly referred to as “Logic Built in self test” (LBIST) circuitry, on the chip itself.
FIG. 1 illustrates a conventional test system 100 including a tester 110 and a device under test (DUT) 120, such as an IC fabricated on a wafer 111, containing LBIST circuitry 130, shown in greater detail in FIG. 2. The tester 110 generally includes any suitable combination of software and hardware configured to initiate LBIST test sequences on the device 120, via an interface 113 (e.g., pins/pads of the device 120). As illustrated, the tester 110 may include test execution software 112 and a set of test data 114 defining a set of test sequences 115. For example, each test sequence 115 may be defined by a set of operations 116 and corresponding data 118 to configure the LBIST circuitry 130 to test the device 120 for a particular type of fault.
As illustrated in FIG. 2, the LBIST circuitry 130 typically includes a pseudo random pattern generator (PRPG) 132 designed to generate test patterns to be applied to inputs of scan chains 134 formed in the circuitry under test 136 and a multiple-input signal register (MISR) 138 to receive signals output from the scan chains 134. An LBIST controller (not shown) generates all necessary waveforms for repeatedly loading pseudorandom patterns from the PRPG into the scan chains 134, initiating a functional cycle (capture cycle), and logging output responses into the MISR 138. The MISR 138 compresses accumulated responses (from multiple cycles) into a code referred to as a signature. Any corruption in the final signature at the end of the test sequence indicates a defect in the device 120. The illustrated LBIST architecture is known as a STUMPS architecture (“Self-test using MISR and Parallel Shift register sequence generator). Such an architecture is described in detail in the commonly owned U.S. Pat. No. 4,503,537, entitled “Parallel Path Self-testing System.”
The scan chains 134 are formed of shift register latches (SRLs) that allow data to be loaded and unloaded in parallel (during a scan mode) to initialize and examine internal circuits that are not externally accessible. During initialization of a test sequence 115 or a portion of a test sequence 115, the tester may load data 118 into one or more of the scan chains 134 via shift register inputs (SRIs) 135, for example, to initialize internal circuitry of the device 120 and/or initialize the PRPG 132 with an initial or “seed” value. At the end of a test sequence 115, the tester may unload data, such as the state of the internal circuitry from the scan chains 134 or a signature from the MISR 138, via one or more shift register outputs (SROs) 137. Signatures unloaded from the MISR 138 at the end of a test sequence 115 may be compared against known good signatures 117 corresponding to that test sequence 115 to detect a fault in the device 120.
While such LBIST circuitry continues to serve the IC industry well, as the number of circuit components increase, designing a set of test sequences 115 that provides adequate assurance that a large percentage of all possible faults are being tested for (commonly referred to as test coverage) becomes increasingly difficult. To ensure adequate test coverage, the number of test sequences 115 is typically increased. For example, there are typically several types or modes of tests (static tests to detect stuck-on/off components, dynamic tests to detect timing related faults, etc.), with several test sequences 115 performed for each type of test resulting in hundreds of test sequences 115. For example, the number of clock cycles may be varied (e.g., from 1 to 8) and/or the number of iterations or “loop count” may be varied (e.g., from 32 to 1 M) each test sequence.
As illustrated, each test sequence 115 may include several full length shift register latch loads. As complex ICs, such as modern micro-processors, may include several hundred-thousand latches, the volume of the test data 114 may quickly grow unwieldy (e.g., several GB). The large volume of the test data 114 may increase test time due to large test data volume transfer and execution, as well as the need for buffer reloading due to buffer size limitations at the tester, which may degrade test throughput and increase test and overall device cost.
Accordingly, a need exists for an improved method and system for performing LBIST testing, preferably that reduces the volume of test data while maintaining adequate test coverage.